Functional Description

The CY7C1350G is a 3.3 V, 128 K × 36 synchronous-pipelined burst SRAM designed specifically to support unlimited true back-to-back read/write operations without the insertion of wait states. The CY7C1350G is equipped with the advanced No Bus Latency™ (NoBL™) logic required to enable consecutive read/write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of the SRAM, especially in systems that require frequent write/read transitions.

Features

■ Pin compatible and functionally equivalent to ZBT™ devices
■ Internally self-timed output buffer control to eliminate the need to use OE
■ Byte write capability
■ 128 K × 36 common I/O architecture
■ 3.3 V power supply (VDD)
■ 2.5 V / 3.3 V I/O power supply (VDDQ)
■ Fast clock-to-output times
❐ 2.8 ns (for 200-MHz device)
■ Clock enable (CEN) pin to suspend operation
■ Synchronous self-timed writes
■ Asynchronous output enable (OE)
■ Available in Pb-free 100-pin TQFP package, Pb-free and non Pb-free 119-ball BGA package
■ Burst capability – linear or interleaved burst order
■ “ZZ” sleep mode option